8 Bit Serial To Parallel Converter Verilog Code

SIPO module sipomod(clk,clear, si, po); input clk, si,clear; output [3:0] po; reg [3:0] tmp; reg [3:0] po; always @(posedge clk) begin if (clear) tmp.

Library IEEE; use IEEE.STD_LOGIC_1164. ALL; use IEEE.STD_LOGIC_ARITH.

ALL; use IEEE.STD_LOGIC_UNSIGNED. ALL; entity P2S is port ( Serial_out: out std_logic; clk: in std_logic; Parallel_data: in std_logic_vector( 15 downto 0); DataReady: in std_logic); end P2S; architecture Behavioral of P2S is signal OldReady: std_logic:= '0'; signal Shreg: std_logic_vector( 15 downto 0); begin process (clk) begin if (clk 'event and clk = '1') then Shreg. Ya input is fixed length of 16 bit but this parallel to serial converter logic should be programmable when ever the data will arrive then dat should get serialized. For example 1st i got the data of 6 bit length at that time that data should be latched then it should get serialized. Similarly some other time when i get the data of length10 bit even in same way that should get serialized. This means our logic should be 1 time programmed instead of runtime programmable.

The above code for serial to parallel converter will working very fine after making a small change in line 11. Instead of using blocking statement if we use nonblocking i.e doutcode (for 33 bit instead of 4 bit)using cadence RC tool and then performed post synthesis simulation using NC launch and i found that this.

I think u got my point. > For example 1st i got the data of 6 bit length at > that time that data should be latched then it should get serialized. > Similarly some other time when i get the data of length10 bit even in > same way that should get serialized. Thats exactly, what my previously posted code does. > 1st i got the data of 6 bit length > some other time when i get the data of length10 bit even in same way And HOW can cou see this difference of 4 bits on a 16 bit vector? How can you KNOW the witdh of the actual vector? > I think u got my point Yes, i do, but not vice versa.

Draw a picture with different parallel input vectors and how the have to occur on the serial output. EDIT: > it is nt simulating Why? Whats the problem? > counter Serial_out. Dft windows installer for htc hd2 free download laptop.